Customize Picoclock Checkers (Software Program)(Ragubalan Shanmugam et al. (Intel, Malaysia), Japan TRIZ Symposium 2009; Introduction by Toru Nakagawa)

TRIZ Paper: Japan TRIZ Symposium 2009
Customize Picoclock Checkers (Software Program)
Ragubalan Shanmugam; Cheng, Chiew Shan (Intel Malaysia)
The Fifth TRIZ Symposium in Japan, Held by Japan TRIZ Society on Sept. 10-12, 2009 at National Women's Education Center, Ranzan-machi, Hiki-gun, Saitama, Japan
Japanese translation of slides by Toshiaki Masaki (Nitto Denko) and Toru Nakagawa (OGU), Introduction by Toru Nakagawa (Osaka Gakuin Univ.), Nov. 28, 2009
[Posted on Sept. 23, 2010]

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Editor's Note (Toru Nakagawa, Sept. 21, 2010)

This is one of the four real case study papers presented by Intel Malaysia last year at the 5th TRIZ Symposium in Japan, 2009. This was presented in an Oral Session.

My introduction to this paper in my "Personal Report of Japan TRIZ Symposium 2009" is written with somewhat unusual starting clause as:

[*** I believe this case study has given a very interesting and useful solution to a confusing problem in an equipment which tests the performance of electric circuit boards. Unfortunately, however, I do not understand well the problem situations and the achieved solution. Reading the Authors' Extended Abstract in 1 page in May, and the Final Presentation Slides at the end of July, I asked the Authors to revise their manuscripts somewhat clearer for non-specialists; but their materials were not revised. So I will use the Authors explanation directly (inside ' '), for the purpose of avoiding from making further confusion. Someday I would like to make a better introduction with the help by the Authors.]

This page is composed as follows:

[1] Extended Abstract by the Authors

[2] Presentation slides in English in PDF ,
Presentation slides in Japanese translation by Toshiaki Masaki (Nitto Denko) and Toru Nakagawa (OGU) in PDF

[3] Nakagawa's introduction in English (Excerpt from "Personal Report of Japan TRIZ Symposium 2009")

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Abstract

Presentation slides

Presentation slides in Japanese

Nakagawa's Introduction

Nakagawa's Personal Report

Japan TRIZ Symposium 2009

Japanese page

[1] Extended Abstract

Customize Picoclock Checkers (Software Program)

Ragubalan Shanmugam; Cheng, Chiew Shan (Intel Malaysia)

Abstract

In Catalyst Tester RF Class Test Operation, pass checkers fail device-“PCFD” has been an intermittent issue. Success of TRIZ in software & electrical issues was proven with applying the Innovative principals to PCFD issue. The 39 parameters and contradiction matrix had helped us to solve the issue that we faced in a structured manner. Innovative principles applied in this project were The Other Way round & Multifunctional. This team drove Teradyne Asia to implement customize checkers program as a new process flow at CEBU repair centre for detail debugging prior to shipment of picoclock boards to Intel. ROI Savings of ~184K USD thru VF factory implementation with zero spending.

Extended Abstract

Background - This abstract discusses the problem solving method which was used in Catalyst Tester Operation which experienced high fallouts of PCFD – ‘Pass Checkers (software Diagnostics) Fail Device. Key challenges in this pursuit involving High Speed Radio Frequency (RF) Test Operations is to be the best in class detecting and eliminating latent failures without compromising Test Yield.

The Problem - PCFD issues have been hitting Catalyst Tester’s as one of the biggest pareto on meeting goal for Tool Utilization, product EUPH, PCS triggering and tool uptime. Pico clock (low jitter clock frequency Generator - Electronics Card) highest failure pareto is Bin Rx71/Tx81 “SNR” signal to noise ratio test. This Electronics Card (PICO Clock) will ‘PASS’ its default supplier tester diagnostics test but fails SNR test during actual HVM test. This fault has bigger impact in downtime and confuses root cause troubleshooting. This is the condition which we call Pass Checker Fail Device issue “PCFD”. CEC analysis shows that the default Catalyst tester diagnostics is not attuned enough to detect latent failures in PICO Clock which ‘PASSES’ the diagnostics but fails the equivalent SNR HVM test on live products. To that end, to make matters worst even the suppliers ‘EXTENDED DIAGNOSTICS’ are unable to detect this form of failures. They often report to us a result of “no fault found” for boards that was sent tagged PCFD.

The Solution – In order to understand further the nature of the problem, we simulated the problem in a controlled DOE (make it worst). Based on these findings a complete CEC and FUNCTIONAL DIAGRAM were developed to understand and define the interactions of the components. After looking through the INVENTIVE PRINCIPLES LIST - “The Other Way Round” was chosen. So based on the ‘output’ we recorded from the DOE, we developed an algorithm of the failure we saw (SNR output). This was then coded into the existing board diagnostics program. So the methodology of a detecting these faults were changed from the earlier ‘test through parametric measurement’ to ‘test by sampling failures’- the other way around! In this way a new generation of diagnostic program was born which is highly sensitive to actual test performance output expectations – based on the products we’re running. An unexpected benefit from this application is the recognition from the supplier themselves that this is the state-of-art method to analyze this board performance and have committed this ‘form’ of analysis for other failures too. For us this has improved our previous single function diagnostics into a ‘Multifunctional’ highly accurate diagnostic tool.

Conclusion – Through TRIZ, 2 innovation principles used, PCFD issue has been successfully resolved – a data driven result! Intel also leads to implement these new diagnostics program and have driven the supplier at repair centre for detail debugging prior to shipment of picoclock boards to Intel. This project has managed to improve tool utilization, product health (retest recovery), reduction of PCS & MTP triggering, MT competency during troubleshooting has improved with better uptime met and ROI study shows positive 42KUSD saved from repair cost with projected 111KUSD savings in next 2years. Proliferation of this concept to VF factory will lead Intel to World Class Test Manufacturing Operation.

[2] Presentation Slides in PDF

Presentation Slides in English in PDF (12 slides, 241 KB)

Presentation Slides in Japanese in PDF (12 slides, 324 KB) (Japanese translation by Toshiaki Masaki and Toru Nakagawa)

[3] Introduction to the Presentation (by Nakagawa)

Excerpt from:
Personal Report of The Fifth TRIZ Symposium in Japan, 2009, Part D. Case Studies in Industries
by Toru Nakagawa (Osaka Gakuin University), Nov. 28, 2009
Posted on Dec. 4, 2009 in "TRIZ Home Page in Japan"

Ragubalan Shanmugam; Cheng, Chiew Shan (Intel, Malaysia) [E06 O-8] gave an Oral presentation with the title of "Customize Picoclock Checkers (Software Program)".

[*** I believe this case study has given a very interesting and useful solution to a confusing problem in an equipment which tests the performance of electric circuit boards. Unfortunately, however, I do not understand well the problem situations and the achieved solution. Reading the Authors' Extended Abstract in 1 page in May, and the Final Presentation Slides at the end of July, I asked the Authors to revise their manuscripts somewhat clearer for non-specialists; but their materials were not revised. So I will use the Authors explanation directly (inside ' '), for the purpose of avoiding from making further confusion. Someday I would like to make a better introduction with the help by the Authors.]

The slide (right) shows the background of the problem. The task to perform is the Mixed Signal Test of some digital circuits. The Pico-clock board supplies the high frequency reference signal voltage to the Tester.

Before reading the explanation of the Problem statement, we should better read the Functional Analysis of the system.

The slide (right) shows the Functional Model of the Picoclock for the Mixed Signal Test of a digital device, i.e., DUT (Device under the test). Receiving the clock signal from the High Speed Digital CC, the Picoclock board sends higher frequency (of pico-second order) reference signal to the DUT.
[*** I do not understand what kind of signal the Picoclock board send (through the Tester) to DUT and what kind of other input signals the DUT receives and what kind of output signals it outputs to the Tester. I do not understand either how the Tester generates the graphs of SNR (Signal to Noise Ratio) shown at the bottom.]
If the SNR value is better than a certain value, the DUT pass the Test.

Now let's read the Authors' explanation of the problem situations with reference to the slide (right) and the next (right-below):

' The Problem - PCFD issues have been hitting Catalyst Tester’s as one of the biggest pareto on meeting goal for Tool Utilization, product EUPH, PCS triggering and tool uptime. Pico clock (low jitter clock frequency Generator - Electronics Card) highest failure pareto is Bin Rx71/Tx81 “SNR” signal to noise ratio test. This Electronics Card (PICO Clock) will ‘PASS’ its default supplier tester diagnostics test but fails SNR test during actual HVM test. '

' This fault has bigger impact in downtime and confuses root cause trouble-shooting. This is the condition which we call Pass Checker Fail Device issue “PCFD”. CEC analysis shows that the default Catalyst tester diagnostics is not attuned enough to detect latent failures in PICO Clock which ‘PASSES’ the diagnostics but fails the equivalent SNR HVM test on live products. To that end, to make matters worst even the suppliers ‘EXTENDED DIAGNOSTICS’ are unable to detect this form of failures. They often report to us a result of “no fault found” for boards that was sent tagged PCFD. '

' The Solution – In order to understand further the nature of the problem, we simulated the problem in a controlled DOE (make it worst). Based on these findings a complete CEC and FUNCTIONAL DIAGRAM were developed to understand and define the interactions of the components.' [*** See the Functional diagram quoted earlier in this review.]

' After looking through the INVENTIVE PRINCIPLES LIST - “The Other Way Round” was chosen. So based on the ‘output’ we recorded from the DOE, we developed an algorithm of the failure we saw (SNR output). This was then coded into the existing board diagnostics program. So the methodology of a detecting these faults were changed from the earlier ‘test through parametric measurement’ to ‘test by sampling failures’- the other way around! '

The slide (right) show the detail of the solution described above.

The significance of this solution is described in the Extended Abstract by the Authors as follows:

' In this way a new generation of diagnostic program was born which is highly sensitive to actual test performance output expectations – based on the products we’re running. An unexpected benefit from this application is the recognition from the supplier themselves that this is the state-of-art method to analyze this board performance and have committed this ‘form’ of analysis for other failures too. For us this has improved our previous single function diagnostics into a ‘Multifunctional’ highly accurate diagnostic tool.'

I will quote the Authors' Conclusion in the Extended Abstract:

' Conclusion – Through TRIZ, 2 innovation principles used, PCFD issue has been successfully resolved – a data driven result! Intel also leads to implement these new diagnostics program and have driven the supplier at repair centre for detail debugging prior to shipment of picoclock boards to Intel. This project has managed to improve tool utilization, product health (retest recovery), reduction of PCS & MTP triggering, MT competency during troubleshooting has improved with better uptime met and ROI study shows positive 42KUSD saved from repair cost with projected 111KUSD savings in next 2years. Proliferation of this concept to VF factory will lead Intel to World Class Test Manufacturing Operation.'

[*** As I mentioned earlier, I do not understand the details of the problem situations and the solutions. But I understand that their 'Outside in' solution is a type of 'Blackbox Test', where the system under test is treated as a blackbox whose behavior is observed from outside without considering/analyzing the inner structure. Because of such a nature of the 'Blackbox Test', it can be applied widely without depending on the detail of the inner structure.]

*** We now have reviewed the four case studies by Intel Malaysia. We should learn that they have been performing these case studies step by step for these several years. The usage of TRIZ tools itself seems rather typical and not so sophisticated. Many of them use the set of 'Technical contradiction - Contradiction Matrix - Inventive Principles'. However, they seem to have obtained good solutions which work well in the real situations of products and processes. We should learn their ways of finding right problems and obtaining right solutions.